Consumer demand continues for increased density integrated circuits, including reduced size processors and logic circuits, and higher capacity memory devices. In an effort to meet such consumer demand, the semiconductor industry continues to pursue advanced technology nodes, in which transistors and other semiconductor devices may be formed with a reduced minimum dimension. Typically, the reduced minimum dimensions refer to the lateral dimensions along the surface of a semiconductor wafer used in the fabrication of the integrated circuits, because two-dimensional semiconductor devices may be conveniently formed using photolithographic patterning and etching steps on the surface of the wafer.
By way of example, a typical SRAM may include six transistors to store a single bit, with the transistors arranged in a particular configuration called an SRAM cell. In addition, an SRAM cell may also include isolation regions to electrically isolate the various transistors. Further, a high density SRAM chip may be formed by repeatedly patterning and forming the SRAM cell design on a wafer, along with affiliated control circuitry. In such a case, the surface area occupied by a single SRAM cell, along with the critical dimensions of the transistors, will determine a limit on the density of the SRAM chip.
Conventionally, two dimensional SRAM cell designs have been used, and as transistor critical dimensions have reduced in advanced technology nodes, the two dimensional designs have been simply scaled down. A need thus exists to further scale down the size of such SRAM cells.